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What does RPCR stand for?

RPCR stands for Receive PHY Control Register

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Other Resources: Acronym Finder has 3 verified definitions for RPCR

Samples in periodicals archive:

6.1 Receive/PHY Control Register;..11 6.2 Memory Information Register...
Frequently Asked Questions; The ANEG bit in the Receive/PHY Control Register and the ANEG_EN bit in the MI PHY Control Register control the Auto-Negotiation mode.
1.3 Receive/PHY Control Register The Memory Configuration Register of the LAN91C100FD has been eliminated and the address used
This is a driver for SMSC's LAN911x series of Ethernet chipsets; + /* Re-Configure the Receive/Phy Control register */ + bmcr &= ~BMCR_PDOWN;
address used for a new Receive/PHY Control Register in the LAN91C111. The Memory Reserved for Transmit, Memory Configuration Register is no longer defined in...
00402 00403 /* Configure the Receive/Phy Control register */ 00404 SMC_SELECT_BANK(ioaddr, 0); 00405 outw( rpc_cur_mode, ioaddr +...
MII_BMCR, bmcr); /* Re-Configure the Receive/Phy Control register */ + SMC_SELECT_BANK(0); SMC_SET_RPC(lp->rpc_cur_mode); + SMC_SELECT...
SMSC LAN91C111 REV C DATASHEET Revision 1.92 (06-27-11); When the ANEG bit in the Receive/PHY Control Register is set and the ANEG_EN bit in the
10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet; Section 8.10 - Bank 0 - Receive/Phy Control Register, page 51 Add Description for SPEED, DPLX, ANEG
Set the ANEG bit to 1 in the Receive/PHY Control Register (MAC Register, Bank 0, Offset A) to enable the Auto_Negotiation mode. 4.
Bank 0 - Receive / PHY control register. #define...
91c111 1. LAN91C111 10/100 Non-PCI Ethernet Single Chip MAC + PHY Datasheet Product Features Single Chip Ethernet; Receive/Phy Control Register...
Bank 0 - Receive / PHY control register. Definition: lanc111.c:231. NIC_FIFO. #define NIC_FIFO. Bank 2 - FIFO ports register. Definition: lanc111.c:304. NIC_TCR.