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What does MAF stand for?

MAF stands for Miss Address File

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DEC Alpha 21164 4-way in-order RISC 32 64-bit 32 Miss Address File: merge outstanding misses to the same L2 line. Instruction Buffer virtually indexed Baer p. 79...
The cache controller 228 also includes a miss address file (MAF) controller 232 and a MAF 234 employed by the MAF controller. The MAF 234 can be implemented as a...
miss address file (not shown) and the result buffer 304. It interfaces with the ISW 302 for purposes of flushing younger loads from the pipe and also to...
(128 entries each), load and store queues (32 commands each), and 8 64-byte buffers (miss address file) for operations with B-cache and main memory.
The uncore 610 may include components such as a miss address file (MAF) 617, victim buffer (VB) 618, and L2 cache (L2) 622.
The 8-entry Miss Address File (MAF) contains all of the in flight cache transactions that are pending on the L2 cache and primary memory.
An onchip, 8-entry miss address file for cache fill requests and I/O read; If you using this document before the 21364 hardware reference manual is...
Each processor further includes a miss address file (MAF) that keeps track of outstanding requests for a memory block not currently stored in the processor's cache.
(CRB), which is a 4-entry 4-port buffer, and which realizes a functionality akin to a miss address file, in order to capture such hits-on-miss...
FIG. 4 illustrates a block diagram of a miss address file (MAF) entry 150 that can be employed to track data fills received in response to a source request.
miss address file 6 data misses 4 instruction stream misses write buffer six 32-byte entries store data s5 s6 s7 96-kb, 64-byte block, 3-way, set-associative
CS 152 Computer Architecture and Engineering www-inst.eecs.berkeley.edu/~cs152/ TA: Eric Love; MISS ADDRESS FILE 6 DATA MISSES 4 INSTRUCTION STREAM MISSES
[0082] Turning now to FIG. 4, a typical entry in the Miss Address File, MAF, 124 A is shown.
The 8-entry miss address file (MAF) holds physical addresses associated with pending Icache and Dcache fill requests and pending I/O space read transactions.
(8Kbyte, write through, non-blocking) On-Chip L2 cache (96Kbyte, 3-way set assoc., write back, pipelined) Miss Address File (MAF), 6 entry...
(in the Miss Address File, MAF) until the corresponding system requests are made and all the missing cache lines are received from their home nodes.
It is possible to indicate the use of a perfect L2 cache. Finally, the size and the number of ports of the Miss Address File (MAF) is user-defined...
RISC versus CISC: A Tale of Two Chips Dileep Bhandarkar; Miss Address File Write Buffer Dual-Read Transaction Buffer Data Cache (DCACHE) TAG DATA Adder Instruction
Consequently, the system posts a miss request in a Miss Address File (MAF). Typically, a MAF will hold a plurality of miss requests. Subsequently...
Alpha: The History in; Alpha 21264 (EV6, EV67; (128 entries each), load and store queues (32 instructions each), also 8 64-byte buffers (miss address file)...
I'm Done Simulating; Now What? Verification Coverage Analysis and Correctness Checking of the DECchip 21164 Alpha microprocessor; miss-address file unit...
analysis and correctness checking techniques that were used. We; miss-address file unit, and a complicated Bus Interface Unit with support for
Cbox Miss-Address File ("CMAF") 174 preferably holds addresses of L1 cache misses. CMAF updates and maintains the status of these addresses.
Alpha 21164PC Microprocessor Hardware Reference Manual; 2.5 Miss Address File and Load-Merging Rules; the Digital Semiconductor Alpha 21164PC microprocessor...
Multi-level Adaptive Prefetching based on Performance Gradient Tracking; Prefetch Miss Address File. Degree controller Prefetch Filters to L1Q or L2Q Inputs MSHRs...
a Miss Address File (MAF) to coalesce pending misses on the same cache block, and the TLB which holds 128 entries and is fully-associative; page size is 8 KB.
Miss Address File (MAF) 6 entry Bus Address File (BAF) 2 entry Addr from integer pipeline 0 Addr from integer pipeline 1. MAF merges loads to the same cache block
write buffer unit, miss-address file unit, and a complicated Bus Interface Unit with support for various CPU-system clock ratios, system configurations...
2.1.4.2 Load Instruction and the Miss Address File The MTU begins the execution of each load instruction by translating the virtual
buffer unit, a miss-address file unit, and a complicated bus interface unit with support for various CPU-system clock ratios, system configurations...
In this instance, the referenced address is placed in a miss address file (MAF) and the fill from the main memory to the dcache proceeds directly.